A 1.2GSPS 6b Low Power Flash ADC in 0.13μm CMOS for Multi- Gigabit Wireless Communication System
نویسندگان
چکیده
A high-speed low-power flash analog-to-digital converter is designed and optimized in a 0.13μm CMOS technology. The ADC consumes 65mW with a supply voltage of 1.2V at 1.2G samples per second. Static DNL and INL are 0.1 LSB and 0.2LSB respectively. The figure of merit shows 1.3pJ per conversion step. The simulation result of the full flash ADC shows improvement in nonlinearity and power dissipation compared to work previously described in the literature. Key-Words: flash ADC, CMOS, Millimetre Wave
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